O: rychlost CHIPRAM v AGA chipsete

AFAIK ChipRam je povestna svou pomalosti, proto mame FASTRam ze ano. Na druhou stranu se mi nezda, ze by 3.5 MHz bylo "na urovni osmibitu". Na kolika Hz bezi pamet v C64? Anebo v Atari ST (i kdyz to je v podstate 4bit)? Nepodarilo se mi vygooglit, rad se necham poucit.

O: rychlost CHIPRAM v AGA chipsete

Ja jsem tedy take myslel, ze CHIP RAM v A500 bezi na stejne frekvenci jak 68000, ale to vazne nevim. Nicmene i v tech osmibitech existuje "chipka", coz je pamet, kde funguje jednak CPU, ale take zakaznicke obvody (obraz, zvuk). Jejich cinnost ma pochopitelne prednost pred vsim ostatnim a jejich pristup pak brzdi pristup CPU, ktere musi cekat, proto se zda, ze CPU bezi pomalu. FAST RAM (v Amize) je pak zapojena primo na sbernici CPU, ktere do ni muze po celou dobu, protoze do ni nemohou zakaznicke obvody.

Prekvapive pamet v Amize (A500/A1200) je vicemene totozna s temi v osmibitech, ale:

1) 68000 pripadne 68020 maji 16/32 bitovou datovou sbernici, takze z te sady pameti ctou 2/4 krat rychleji nez ten osmibit.

2) Vcetne 2 nebo 4x vyssiho taktu uz to dela radovy rozdil.

Nevim jestli si to pamatuji spravne, ale Z80 v ZX Spectru ma tusim cca 0.5 MIPS a 68000 v A500 asi 1 MIPS, coz je trochu matouci, protoze ta A500 vypada oproti ZXS jako z jineho vesmiru. Jenze to je pocet instrukci za sekundu a v Amize je ta "sila" predevsim v zakaznickych obvodech a pak 68000 ma instrukce vnitrne 32bit (sbernice je 16bit), takze zpracuje podstatne vicet dat pri stejnem poctu instrukci.

Proto ten rozdil je tak velky i kdyz ty cisla kolem vypada srovnatelna.

O: rychlost CHIPRAM v AGA chipsete

Graficky cip VIC-II v C64 je dabelsky rychly, ked som prvy krat hral strielacku Zynaps plus v roku 1991 na C64 teda padla mi sanka,
aj prerabka tejto hry na Amige sa absolutne nechyta na verziu C64.



The VIC-II runs at a frequency which is exactly 8 times that of the CPU

O: rychlost CHIPRAM v AGA chipsete

ZX spectrum má tiež 3.5Mhz a to CPU aj pamäť aj keď prístup je len cez 8 bitovú dátovú zbernicu. Čakal by som, že na amige 500 bude mať chipram tých 7.14 MHz, je to a frekvencia jej procesuru, ak by pristupoval CPU do pamate s polovičným taktom, dizajneri by si skomplikovali návrh.

O: rychlost CHIPRAM v AGA chipsete

Zákaznícke obvody a CPU sa musia deliť o spoločnú pamať, ak tá je pomalá, tak je celý systém pomalý. Vďaka za FASTRAM, tvorcovia amigy vedeli, že s tým bude problém v budúcnosti.

O: rychlost CHIPRAM v AGA chipsete

Tu: https://en.wikipedia.org/wiki/Amiga_Chip_RAM a tu: https://retrocomputing.stackexchange...mory-bandwidth je to vysvetlene, predstavu o casovani ti to da.

Toto je asi najpodrobnejsie vysvetlenie principu casovania v Amige:

To understand how Amiga memory bandwith should be calculated and how data fetching to Amiga Chipram works.
The timingslot schematic that rwallace refering to does not tell anything about how individual chipram ic' operates or are supposed to operate; it just explains how the Amiga timing system is layed out.
The Amiga is a synchronized multiprocessor platform/architecture. It share same memory to some extension. That shared memory is called chipram. The shared memory require some rules to be followed to make it work and to avoid something called bus contention. Bus contention occurs when more than one processor want access to the common address-, data-, or registerbus.
To solve this Amiga has a nested (interleaved) access to the buses (and some other solutions too). It means that the bus access is divided into odd and even timeslots. The whole timeslot concept is based on duration of one video raster-scanline, and that one timslot has a duration of approximatly 280ns. Why 280ns? Because it's the speed of the color clock driving the amiga chipset (Agnus, Paula, and Denise. Agnus contains the DMA controller responsible for memory access to chipram).
1000 000 000 / 3546895hz (colorclock) = 281.9367ns (PAL)
Due to the interleave approach to solve the bus contention problem the individual processors does not fetch data from chip memory with a bandwidth of 7mb/s but instead half of that amount - 3.5mb/s. Now this it not the whole truth. In graphic intensive tasks the amiga chipset can take full control of the buses and run at full bandwidth (7mb/s) at the expense of the cpu not having any access at all (no timeslots to its disposal). The DMA sytem can also be turned off and let the cpu have full access and do all the work (every other timeslot that is). Note: horisontal and vertical blanking period is not included in these situations.
To calculate the memory bandwidth for the cpu (mc68000):
Following calculations applies to OCS/ECS (16-bit) chipset:

1. Master clock (MC): 28.37516Mhz (PAL), 28.63636Mhz (NTSC)
2. Color ClocK (CCK): MC/8 = 3.546895Mhz (PAL), 3.579545Mhz (NTSC)
3. CPU speed is (MC/4): 7.093790Mhz (PAL), 7.159090Mhz (NTSC)
4. It takes 4 cpu cycles for main cpu (Motorola 68000) to fetch data from external memory (Fast or Chip mem) -->

7.093790Mhz / 4 = 1.773448Mhz (PAL),
7.159090Mhz / 4 = 1.789773Mhz (NTSC)

1. Bandwidth:

1.773448Mhz * 2byte = 3.546895mb/s (PAL)
1.789773Mhz * 2byte = 3.579545mb/s (NTSC)
It actually takes 560ns - two time slots (one time slot being 280ns) for cpu to fetch data from memory (Fast OR Chip mem).
An example:
(PAL)

• 1000 000 000 / 7093790Mhz = 140.96837ns
• 140.96837ns * 4 cpu clockcycles = 563.87347ns

How much is the different clock-speeds in terms of nanoseconds (ns)?
Always divide the (Mhz) by 1000 000 000 (1000 000 000 / Mhz) and you will get ns. When you read the inscription on memory ic's the access speed is written in nanoseconds e.g. 41256-15 means 150ns (access time).
To increase bandwidth to chip memory three 'rules' must be fulfilled:

1. Cpu clock need to be synchronized with masterclock.
2. Chip memory need to be fast enough to handle the new clockspeed.
3. The cpu clock need to be at least four times as fast, i.e. at the same speed as masterclock to double the bandwidth. The synchronization require cpu clock to be a multiple of masterclock.

Why does cpu need to be four times as fast to increase the bandwith? Because of the interleaved approach to chipram between cpu and amiga chipset; this together with the fact that - as mentioned above - it takes 4 cpu clock cycles to fetch data from chipram (and fastram). In other words; cpu access chipram (and chipregisters) every other timeslot and therefore it needs to be quadrupled in clockspeed.
NOTE: This will only increase bandwidth between cpu <-> chip-ram and not the speed between Amiga Chipset <-> chip-ram.

O: rychlost CHIPRAM v AGA chipsete

mna by este zaujimalo, ako je synchronizovany pristup CPU do Chip-ram u turbokariet, kde CPU ma svoj vlastny oscilator, asynchronny voci masterclock oscilatoru, ktory taktuje cely cipset. To by nam mohol trochu objasnit Boboo, kedze pri navrhu Furie sa s tym potykal.
Diky Boboo

O: rychlost CHIPRAM v AGA chipsete

Tady z těch výpočtů mě zaujalo jedno:

konkrétně "CPU speed is (MC/4):". Není to spíš obráceně, že MC je CPU speed x 4? Protože imo napřed byl na trhu procesor, vyráběný Motorolou na nějakém taktu a nad ním se pak stavěl hardware Amigy a podle něj se počítal MC a takt zákaznických chipů, ne? Nebo to špatně chápu a MC68000 se dá podle potřeby taktovat až při návrhu desky a ten vypočítaný MC/4 takt se jí vnutí? Což se mi úplně nezdá, protože jsem viděl prodávat MC68000/10 MHz, která se údajně dá dát v pohodě do pětikule a trochu jí zrychlí (i když pak má některý SW problém se stabilitou).

O: rychlost CHIPRAM v AGA chipsete

CPU clock je odvodeny z MasterClocku. Je to jasne vidiet aj na scheme A500. Oscilator 28 MHz vstupuje do Agnusu a z neho ide von mimo ine aj MC/4 - 7 MHz pre CPU. Pointa je, ze hlavny bus arbiter je prave Agnus, preto vyraba vsetky clocky pre ostatne cipy. Prioritu maju vzdy DMA kanaly (obraz, zvuk, blitter...), CPU je az na poslednom mieste. Agnus/Denise moze kradnut CPU cykly pre DMA kanaly ako potrebuje, preto su Hi-Res a SHi-Res rezimy bez Fastram take pomale.
Rovnako to bolo aj v C64, tam generoval vsetky clocky cip VIC.

O: rychlost CHIPRAM v AGA chipsete

Ano toto su dovody preco su Hires rezimy tak priserne pomale (hlavne pri vacsom pocte farieb) na A1200, z toho som bol velmi sklamany ked som si kedysi A1200 kupil.

O: rychlost CHIPRAM v AGA chipsete

Takže CPU efektívne pristupuje do chipram s frekvenciou 1.773448Mhz u PAL amigy, keďže môže použiť len v každom druhom takte. Teda som mal pravdu, že chipram má frekvenciu približne 3.5 Mhz.